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This is another keyer design. The thing that separated this keyer from the others, is that it was not published in any magazine. This keyer was manufactured and sold by H. Alan Harp, K4PB. And he made a lot of them. The schematic below is a redraw from H. Alan Harp's User Manual for his "CW Sendin' Machine".
Initially, I scanned over the user manual and didn't see anything really exciting. The paddle input circuitry was common among many keyers, and there are only so many ways that you can include memory. So I thought I would just redraw the schematic and leave it at that.
In the original schematic, gates were draw as gates. However, higher level logic, like Flip-Flops, Counters, and Rams were drawn as empty boxes with pin numbers. I did like the fact that K4PB used Demorgan Equivalents, with the gates, but the empty boxes took a bit of deciphering. As I was resolving some of the devices, I came across a SN7474 D-Type Flip-Flop (U15B on Page 2 below) that was configured oddly. On the right is a isolated drawing of that Flip-Flop.
- The PRE input is grounded.
- The Q output is wired back to the CLK and D inputs and used as a CLR signal on the other timing Flip-Flops (U16-A, U16-B, U15-A).
- Then a Keyer Clock (CLK) is applied to the CLR input.
- The Q is used to clock the RAM address counters.
FUNCTION TABLE | |||||
---|---|---|---|---|---|
INPUTS | OUTPUTS | ||||
PRE | CLR | CLK | D | Q | Q |
L | H | X | X | H | L |
H | L | X | X | L | H |
L | L | X | X | H↑ | H↑ |
H | H | ↑ | H | H | L |
H | H | ↑ | L | L | H |
H | H | L | X | Q0 | Q0 |
Now, I'm not sure I have ever seen a Flip-Flop configured that way. However, when I looked at the FUNCTION TABLE in the spec sheet, there is a entry that covers this configuration. I have listed the table from the spec, and then highlighted the entry in BLUE. This entry shows that when the PRE and CLR are both held "LOW", the Q and Q outputs both go HIGH.
There is a note on this particular state, that this configuration is nonstable and the output levels will not persist when either PRE or CLR returns to it's active (HIGH) level. But that is what we are counting on. If the CLR return to a HIGH level, as shown in the PINK highlighted entry, the Q will go LOW. So if we toggle the CLR from LOW to HIGH, the Q will toggle in the reverse.
Note that the address lines (A00 throu A09) going in to the RAMs (U1 and U3) do not match the address labels. I adjusted these addresses to correspond to the original schematic in the User Manual. In the end, it makes no difference as to the order of the address lines. Address lines were often swapped around to make printed circuit layout easier.
This is a list or Errors or oversights that show up in the CW Sendin' Machine User Manual.
- On all sheets, ICs are empty boxes, with only pin numbers to aid in deciphering their function.
- On Sheet 2, U1 has pin 13 listed twice. It is correct in the drawings above
- On Sheet 2, U3 lists pin 9 as one of the address pins. Pin 9 is the VSS (Ground) pin. The correct pin number should be 7. It is correct in the drawings above
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